HDI Technology

• Surface real estate
• Signal isolation
• Reduced signal antenna (less noise)
• Different component footprints top to bottom
• Robust PCB manufacturing and long-term board reliability on µBGAs (≤0.5mm)

• Real estate – frees up surface routing
• Different component footprints on top & bottom side
• Reduce signal stubs/antennas
• Isolation – keep nets separate
• Clean ground loops for RF

• Registration (thru drill to blind vias)
• Extra plating on board surface
• Must be filled (prepreg or resin-filled - can be via-in-pad/Plated Over Filled Via (POFV)
• Extra processing time for sub lam portion

A blind via does not pass through the entire board, and has access to only one external layer

• Real estate – essential for pinout of most microBGA devices (<0.65mm)
• Clean ground loops for RF and capacitor pads
• Mechanical rivet for extra pad stability
• Thermal dissipation (Cu-filled microvias)

• Extra plating on board surface if resin-filled for via-in-pad (POFV)
• Aspect ratio must be less than 1:1 (best manufacturability when ≤0.85:1)

• Real estate – frees up surface routing
• Isolation – keep nets separate
• Essential for pinout of most microBGA devices (<0.65mm)
• Buried vias in combination with microvias give several drill span options (example on next slide)

• Registration
• No direct test point access for ICT
• Must be filled (prepreg or resin-filled)
• Adds plating to outermost internal layers
• Extra processing time for sub lam portion

A buried via provides connection within internal layers, and has no access to external layers

• One layer of 4 mil microvias dogboned in 10 mil pads (30% cost adder) or via-in-pad (additional 10% cost adder)
• Standard 10/20 thru vias (no cost adder)
• M4-5 mil trace & space (no cost adder)
• Consistent, high yields
• Standard drill to Cu on internal layers - No CAF risk

• Many device white papers suggest a 6 mil thru drill in a 10 mil BGA pad (6 mil drill is a 20% cost adder)
• Resin-filled vias needed for via-in-pad (10% cost adder)
• Traces between pads are 3.0 mil trace / 3.3 mil space (yield reduction by up to 50%, inconsistent yields lot to lot)
• Minor soldermask misregistration will expose trace edge (shorts under device causing assembly rework or scrap)
• Drill to Cu on internal layers too tight for CAF (increased potential for field failures)

• Resin-filled vias are encapsulated completely in the solderable pad
• Pad will look like a normal BGA or SMT pad when viewed from the board surface
• Soldermask can be tented or clearance, same as can be applied to solderable pads
• Resin filled vias add extra plating to the board surface which needs to be etched through
• Designs with resin-filled vias require extra spacing (.005” min spacing) for best manufacturability

• Real estate – frees up surface routing
• Pinout of dense microBGA devices (≤0.5mm) for reliability and manufacturability

• Must be filled (resin or Cu filled/plated shut)
• Stacking microvias on buried vias can be a reliability concern on boards >.062” thick (> .093” is greatest risk) due to Z-axis thermal expansion
• No concern with stacking microvias on top of each other
• Staggered microvias should be .008” min from edge of microvia to the edge of the buried via

Starting Cu weight on all plated layers to be 0.33oz

* Larger pad size on the thru vias helps with registration if real estate allows

** Aspect ratio is total laminate and Cu thickness (including starting foil thickness)/min hole size diameter

***Use the center of the drill/pad for stacked structures